1. Field of the Invention
The present invention relates to a multilayer capacitor designed to reduce the equivalent serial inductance (ESL), more particularly relates to a multilayer ceramic chip capacitor enabling three-dimensional mounting.
2. Description of the Related Art
Capacitors have conventionally been broadly used as one type of electronic device. Due to the demands for high density mounting etc. in recent years, compact multilayer ceramic chip capacitors have also come into use.
A general multilayer ceramic chip capacitor has for example a capacitor body formed in a rectangular parallelopiped shape and internal electrodes alternately superposed to face each other inside the body. The internal electrodes are designed to be able to obtain an electrostatic capacity due to the ceramic layer positioned between them. The two ends of the capacitor body in the longitudinal direction are formed with terminal electrodes. These terminal electrodes are connected to the alternately arranged internal electrodes. The internal electrodes are connected to the terminal electrodes in an manner extending in a perpendicular direction.
Further, known in the art are multilayer ceramic chip capacitors such as three-terminal through-hole type capacitors and flip-type capacitors which reduce the parasitic inductance and the ESL by means of the internal structure and the arrangement of terminal electrodes. Even a multilayer ceramic chip capacitor reduced in ESL however has internal electrodes connected to the terminal electrodes in a form extending in the perpendicular direction.
In recent years, the increase in the operating frequency accompanying higher speeds of operation of CPUs has meant that even multilayer ceramic chip capacitors lowered in ESL in use up to now sometimes have too large a parasitic inductance. Further, conventional multilayer ceramic chip capacitors have all been connected to the boards by soldering, so that the capacitors have had the defect that the inductances of the lands between devices ended up becoming larger.
On the other hand, along with the increase in the operating frequency of CPUs, when the equivalent serial resistance (ESR) in an electronic device is large, the heat buildup of the electronic device itself becomes large and therefore the heat buildup becomes a problem.
Note that as shown in Japanese Unexamined Patent Publication (Kokai) No. 6-275463, Japanese Unexamined Patent Publication (Kokai) No. 6-267790, and Japanese Unexamined Patent Publication (Kokai) No. 7-169649, multilayer through-hole type capacitor arrays having through-hole electrode structures have been proposed. In the capacitor arrays described in these publications, while through-hole type electrodes are disclosed, adjoining external electrodes are the same polarity (ground terminal is provided at the body end), the flows of currents at the through-hole terminals and ground terminals do not act to cancel each other out, so that there is the problem that reduction of the ESL is difficult.
Further, the magnitude of the ESR of a capacitor having a through-hole electrode structure is determined by the width, length, and number of columnar internal electrodes due to the through-holes and the state of connection between the internal electrodes and external electrodes. Further, in general, columnar electrodes are easily roughened due to problems in production, therefore there is the defect that the junctions with the external electrodes become unstable and the ESR tends to become large.
An object of the present invention is to provide a multilayer capacitor designed to reduce the ESL even more and enable three-dimensional mounting.
To achieve the object, the multilayer capacitor of the present invention comprises a planar first internal electrode arranged in a capacitor body formed by stacking dielectric layers; a planar second internal electrode arranged facing the first internal electrode separated by the dielectric layer in the capacitor body; a first through-hole electrode connected with said first internal electrode and passing through a second non-contact hole of said second internal electrode while extending to intersect both of the internal electrodes; a second through-hole electrode connected with said second internal electrode and passing through a first non-contact hole of said first internal electrode while extending to intersect both of the internal electrodes; first external electrodes connected to said first through-hole electrode and arranged in island shapes on two surfaces of the capacitor body; and second external electrodes connected to said second through-hole electrode and arranged in island shapes on two surfaces of the capacitor body.
According to the multilayer capacitor of the present invention, the first external electrodes and second external electrodes are arranged on flat portions forming surfaces of the capacitor body. The two types of the first and second through-hole electrodes connected respectively to the two types of internal electrodes extend in columnar shapes into the thickness direction of the body from the external electrodes. Further, these two types of through-hole electrodes alternately become positive and negative polarities at the time of carrying a current and act as electrodes for the two types of internal electrodes arranged in parallel in this capacitor.
The multilayer capacitor according to the present invention is used as a smoothing capacitor for an IC power source. It is buried in a multilayer board of a three-dimensional structure for a microprocessing unit (MPU) and is connected from the top and bottom. Further, the IC power source has a Vcc terminal and a GND terminal. High frequency currents flow in opposite directions to lands arranged three-dimensionally in the board.
Therefore, the magnetic fields cancel each other out due to the high frequency currents flowing in the opposite directions, so that the loop inductance of the board is reduced. Further, there is naturally the effect that the lengths of the lands themselves become shorter due to making the board three-dimensional.
On the other hand, inside the multilayer capacitor as well, two types of columnar through-hole electrodes provide the above three-dimensional effect of the magnetic fields canceling each other out due to the high frequency currents flowing in opposite directions. Further, since the positive and negative currents intersect two-dimensionally between the two types of internal electrodes, the parasitic inductance of the multilayer capacitor itself is sharply reduced.
Due to the above, in the capacitor according to the present invention, the two types of through-hole electrodes are formed in columnar shapes and are connected alternately to the two types of internal electrodes, so that it is able to be mounted three-dimensionally on a board. Also, it is possible to reduce the loop inductance of the board itself three-dimensionally and reduce the parasitic inductance of the multilayer capacitor itself not only two-dimensionally, but also three-dimensionally by the effect of cancellation of the magnetic fields.
In the present invention, preferably the first external electrodes and second external electrodes are arranged on the surfaces of the capacitor body so that the first external electrodes and the second external electrodes are next to each other and a plurality of lines of these external electrodes are arranged. In this case, since a plurality of first external electrodes and second external electrodes are arranged next to each other, the effect of the magnetic fields canceling each other out due to the high frequency currents flowing in opposite directions is further enhanced.
In the present invention, preferably the capacitor body is formed in a hexagonal shape; first terminal electrodes connected to said first internal electrode are formed at least at three side faces of the capacitor body; and second terminal electrodes connected to said second internal electrode are formed at least at three side faces of the capacitor body.
In this case, lead electrodes of the facing internal electrodes are lead out alternately to at least three side faces. Further, in the same way as a conventional capacitor array with terminal electrodes arranged at the side faces, terminal electrodes are arranged at the side faces of the body and the internal electrodes led to the terminal electrodes are connected. Therefore, external electrodes and terminal electrodes are formed on all six faces of the multilayer capacitor made a rectangular parallelopiped and therefore not only three-dimensional mounting, but also two-dimensional mounting becomes possible. As a result, when supplying high frequency currents to the terminal electrodes so that the terminal electrodes of the side faces alternately become positive and negative and supplying high frequency currents to the two types of external electrodes to become alternately positive and negative, opposite currents flow to the columnar through-hole electrodes. Therefore, the currents intersect so that the two types of internal electrodes connected to the terminal electrodes and through-hole electrodes become positive and negative polarities and as a result the parasitic inductance further falls and the ESR and ESL can be further reduced.
In the present invention, preferably the first through-hole electrode and the second through-hole electrode are formed by nickel or a nickel alloy. By using a shrink-resistant nickel-based metal with a low specific resistance as the material of the through-hole electrodes, it becomes possible to maintain good junctions with the internal electrodes and keep the ESR low.
In the present invention, preferably the first internal electrode and the second internal electrode are formed by nickel or a nickel alloy. By making not only the material of the through-hole electrodes, but also the material of the internal electrodes a nickel-based metal, the junction property between the through-hole electrodes and the internal electrodes becomes higher and the ESR can be kept lower much more reliably.